1. Field of the Invention
The present invention relates generally to semiconductor manufacturing and, more particularly, to methods of and apparatus for pre-planarizing a substrate in order to more efficiently perform a planarization operation.
2. Description of the Related Art
During copper interconnect manufacturing, a copper layer is deposited on a seed/barrier layer using an electroplating process. Components in the electroplating solution provide for appropriate gap fill on sub-micron features. However, these sub-micron features tend to plate faster than bulk areas and larger, i.e., greater than 1 μm, trench regions. Regions of the sub-micron features are typically found in large memory arrays such as, for example, static random access memory (SRAM). These array regions can comprise large areas of the wafer. The topography resulting from the electroplating process may be referred to as the “copper topography”, and is not suitable to receive further layers without being planarized. Also, it should be appreciated that such large-area array regions have additional copper topography that must be planarized in addition to required planarization of the larger trench regions.
FIG. 1 is a simplified schematic diagram illustrating a silicon substrate 100 having a copper layer 102 deposited thereon. Copper layer 102 is deposited on a seed/barrier layer 104 disposed over the silicon wafer 100 using an electroplating process. As mentioned above, components in the electroplating solution provide for good gap fill on submicron features, such as sub-micron trenches in regions 104a and 104b, but these features tend to plate faster than the bulk areas and trench regions 106a–d. The faster plating results in undesirable “steps” in the copper topography on the substrate, illustrated by regions 108a and 108b, over the sub-micron trench regions. Thus, these large area regions (e.g., 108a), which step up in height, must be planarized along with the copper topography over the trench regions 106a–d. Exacerbating this situation is that the silicon wafer 100 itself has an inherent waviness (nanotopography) introduced during the silicon wafer manufacturing process (e.g., using wire saw, lapping, polishing). Because of the waviness, the surface of the silicon wafer that receives the seed/barrier layer 102 (and which underlies the layer 104 and the copper layer 102) is not perfectly flat. The wafer is said to have a “wavy topography”, or “contour”, and this contour may extend across the entire wafer surface. FIG. 1 shows a peak 109P and a valley 109V of such contour.
Current planarization techniques are not suited to properly planarize such copper topography resulting from the electroplating process. For example, such planarization techniques are sensitive to pattern density and circuit layout. More specifically, chemical mechanical planarization (CMP) processes must be “tuned” based on upon properties of the incoming wafer properties to be processed. By this tuning, changes are made to the CMP process, such as changing consumables (pad and slurry) in order to accommodate variations within lots (or batches) of the incoming wafers. Such changes also are made to accommodate different pattern densities and circuit layouts on incoming wafers that are typical of mixed-product manufacturing lines. When attempting to perform a single CMP process on such copper topography without changing the consumables, attempts to completely remove the copper from regions 108a and 108b result in excessive dishing and erosion over trench regions 106a–d. Additionally, not only must the CMP process remove the excess copper in regions 108a and 108b, but the CMP process must also perform this removal in a manner that follows the contour of the substrate. Current CMP processes do not suitably deal with both of these variables.
Another limitation of current CMP processes and related equipment is that the spindle that carries the wafer for processing is not designed for accurate Z axis motion. Instead, the substrate is pressed against the polish pad and the pad is engineered with a hardness that allows it to follow the contours of the wafer. This allows short-to-medium range planarization distances (0.16–200 um), but not long-range planarization distances (1–5 mm).
Further, the effectiveness of existing metrology used to control such current CMP processing is limited to average measurements that extrapolate a measurement site to other sites that are not measured. The accuracy of the extrapolation may be reduced by structure and consumables used with current CMP processing equipment. These include, for example, endless belts that engage the wafer and interfere with viewing or other monitoring of the planarizing activity by metrology apparatus. Also, many CMP slurries are thick and not optically clear, for example, which tends to further interfere with viewing or other monitoring of the planarizing activity by the metrology apparatus.
As compared to such CMP processing, known wafer grinding equipment has accurate Z axis control. However, in the past the object of such wafer grinding equipment has been to produce an absolutely flat wafer surface. By definition, such wafer grinding equipment does not follow the wafer contour, because that contour is to be eliminated in producing the absolutely flat wafer surface. Further, because the sensitivity (or resolution) required for following the wafer contour is in the submicron range of Z motion, stepping motors, for example, may possibly be inadequate for providing Z axis motion in submicron increments. In any event, such motors, x-y stages and substrate chucks are relatively costly.
Despite these disadvantages of wafer grinding techniques, efforts relating to development of embodiments of the present invention have included attempts to apply wafer grinding techniques to wafers having a copper topography, as defined above. In one such approach, a horizontal grinding ring is provided with segmented compliant layers. The ring has a large diameter (e.g., of 12–14 inches) and thus extends across a large area of the wafer (e.g., 8–12 inches, depending on the substrate diameter) during grinding. Each segmented layer is provided with abrasive materials that are pressed into contact with the copper topography of the wafer to scratch the copper topography. These attempts to apply wafer grinding techniques to wafers having the copper topography have advantages of higher average removal rates, for example. However, simplification of the horizontal grinding ring for such purposes as cost-reduction and increasing ability to provide Z height control in the submicron range, remain as objectives. Also, it would be desirable to provide further simplification to reduce interference with real-time in-situ viewing or other monitoring of the grinding activity by metrology apparatus.
In view of the foregoing, there is a need for methods of and apparatus for normalizing the surface of a substrate to be planarized in order to more efficiently perform planarization processes. Such need includes removing the excess copper in regions 108a and 108b while following the wavy contour of the substrate, which would normalize the wafer surface to provide a uniform thickness of the copper film regardless of height changes of the wavy contour of the wafer surface or the initial topography of the copper film. Such need further includes normalizing that is independent of other properties of the incoming wafer properties to be processed, e.g., pattern density and circuit layout, such that there can be minimal or reduced changes in the consumables or process parameters used for CMP processing after normalizing. Such need additionally requires providing a relatively low-cost way to provide highly accurate (in a nanometer range) Z motion of a tool relative to a surface of a wafer. Such need further includes performing normalizing without interfering with viewing or other monitoring of the normalizing activity by metrology apparatus.